fast aid converter ..' adc1103 . features high speed 8 bits in 1.0/-is max 10 bits in 1.5~s max 12 bits in 3.5/-1s max error relative to full scale :t1lsb max gain tc :t10ppmfc max user choice of three input ranges small 2" x 4" x 0.75" module 8 general description the adcll03 is a hi~h speed analog-to-digital converter packaged in a small 2' x 4" x 0.75" module. it is available in 8, 10, and 12 bit versions. the 8 bit model performs a conversion in 1.0~s max, the 10 bit version in 1.5~s max, and the 12 bit unit in 3.5/-1s max, the adcll03 uses the successive approxi- mations technique to convert analog input voltages into natural binary, offset binary, or two's complement coded parallel out- put digital data. careful design and the use of schottky ttl have resulted in a very fast a/d converter that features an error relative to full scale of only :tllsb max. the unit has a maximum gain tc of only :tl0ppm/c. three analog input ranges are available. the user, with connec- tions at the module pins, can select the 0 to +10v range, the -5v to +5v range, or the -10v to +lov range. when using the 0 to +10v range, the output coding is natural binary. how- ever, when using either the -5v to +5v range or the -10v to +lov range, either offset binary or two's complement coding can be selected. the user can also choose to short cycle the converter (i.e., have it perform conversions of less than the maximum number of bits). applications the adcll03 is a general purpose fast aid converter. it is especially well suited for applications requiring high through- put rates with no compromise in accuracy. a typical application would be a multiple channel data acquisition system, where a high throughput rate/channel is needed. the adcll03's high speed makes it an excellent choice for such applications as fast fourier transform analysis, radar pulse analysis, conversion of analog data acquired from simultaneous sample-and-hold data collection systems, and for conversion of analog data to be fed into digital filters and correlators. . information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. -- -- timing as shown in figure 1, the status output is set to a logic" 1 " on the leading edge of the convert command pulse. on the trailing edge of the convert command pulse, the msb output is set to a logic "1", the remaining bit outputs are set to "0", and the conversion commences. the output data is valid 4ns prior to the "1" to "0" transition of the status output (or "0" to "1" transition of the status output). this set-up time is sufficient to allow the output data to be strobed into a following schottky ttl register on either of these two edges. if a standard ttl register is used, data should not be strobed into it until at least 16ns after the status and status transitions occur. the serial data output (which does not appear on the standard unit) is of the nonreturn-to-zero type (nrz). the data is available, msb first, on successive "0" to "1" data strobe transitions. ~~ ha - -- - "i<,"'w_w",-c-, i&i specifications resolution aocii03-oo1 aocll03-oo2 aocii03-oo3 conversion time aocll03-oo1 aocii03-{)02 aocll03-{)03 accuracy 1 error relative to full scale2 quantization error differential nonlinearity error2 missing codesj temperature coefficients gain tc zero tc (unipolar input) (bipolar input) differential nonlinearity tg input voltage ranges input impedance 0 to +lov and :tsv ranges :tl0v range convert command ",-,-' ~-,- (typical @ +25c and nominal supply voltages, unless otherwise noted) outline dimensions dimensions shown in inches and (mm). 8 bits 10 bits 12 bits 1.0j.ls, max l.sj.is, max 3.sj.is, max :tllsb max :t~lsb max :tllsb max no missing codes from 0 to +70c :tl0ppm/c of reading, max :tsppm/c of full scale, max :tl0ppm/c of range, max :tsppm/c of range, max 0 to +10v, :tl0v, :tsv 2.s0k ohms s.ook ohms positive pulse, 50ns min width, ips max rise and fall times, til compatible parallel data output with unipolar input range with bipolar input range serial data output4 status output logic fanouts and loadings convert command input parallel data outputs status output status output serial data output4 clock inhibit input data strobe output4 adjustments zero (or offset) gain power requirements power supply sensitivitys temperature range operating storage prices (1-9) adcllo3-{)oi adci103-{)o2 adcii03-{)o3 positive true binary positive true offset binary or two's complement bits valid on successive "0" to "1" transitions of data strobe pulses, with msb fitst. til compatible. "1" during conversion. complement also available. ttl com.atible. 5 til unit loads 8 til unit loadslbit 8 til unit loads 8 til unit loads 8 til unit loads 1 ttl unit load 8 ttl unit loads external look ohm potentiometer across :t15v with slider to pin 46. external look ohm potentiometer across :t15v with slider to pin 70. +15vdc :t3% @ 85ma max -15vdc :t3% @ -80ma max +5vdc :t5% @ 525ma max :to.003%/%6. v (:t15v only) typical :to.007%/%6. v (:t15v only) max 0 to +70oc -55c to +125c $473. $484. m95. , warm-up rime to tated accutacy is s minutes. 'ti>lsb fot the adc1l03.()()1 and adc1l03'()()2. 'except the adcl1o3.()()3 which is guaranteed to have no missing codes at +2soc. 'tne standard unit does not have a serial output, or a dart strobe output. contact the factory fot price and availability of models with serial output. 'this specification is valid only when the + 1 sv supply tracks the -i sv supply (or vice versa). specifications suhject to change without notice. -- --~- -~ - - ~ ~- - -2- r'~- 151'31---i i t 0,77 max, iis,8) ~min' --'-15,01 . 38 37 ~ ~ z 0 ;:: " z '" u; ~ z 0 ;:: .. 0 ~ 0 n ~ 54 ..... 55 >< " :; n 0 .. 18 72 80ttom view -11- grid or 12.51 note: terminal pins installed only in shaded hole locations. all pins are 0.019" :to.001" (0.48mm :to.03mml dia. half-hard brass, gold plated per mil-g-45204b, class i, typel!. for plug-in mounting card, order board no. ac1549 @ $25.00. 8 block diagram and pin designations oigital~:~ ; i ~ -15v . 0-- 72 ~~7s':rr 70 gain aoj bit 1 imsb, 10 ., oata strobe sa ~~al oata 55 analog gro so sig gro sense '9 comp in .a input 2 '7 input 1 .a offset aoj '2 convert cmo sit 12 34 39 status 3a rnrus 37 cli< inhibit note: the standard model does not have a serial output, and therefore pins 58 and 61 are deleted from it. the adc 11 03c-qo2 does not contain pins 32 and 34. the adc1103-001 does not contain pins 27, 30,32 and 34. 8 --- --- obsolete
. . applyingtheaqc1103 .' . analog signal input connections the adc1103 offers a choice of three input ranges, any of which may be selected by the user. the table below shows the connections required for each range. input range selection . also connect a 3.0k.l1 :1:5% resistor between pin 72 and pins 54 and 55. signal ground sense (pin 50) should normally be jumpered to analog ground (pins 54 and 55). however, in the event there is an offset in the ground wiring, it may be possible to eliminate it by connecting pin 50 instead directly to the signal or analog ground of the device feeding the analog input signal to the adc1103. in any case, pin 50 must not be left open with nothing connected to it. if a high input impedance is required, it can be achieved by using a high speed operational amplifier as an input buffer. analog devices' model 48 fast settling differential amplifier, packaged in a small 1.125" x 1.125" x 0.4" module, is an ideal choice. 8 output coding when using the 0 to +10v range, the ouput coding is natural binary, positive true. when using the :!:5v or :!:10v ranges, the coding can be either positive true offset binary or positive true two's complement at the user's option. the only difference between the two codes is the state of the msb. the msb out- put (pin 10) is used for offset binary coding, while the msb output (pin 8) is used for two's complement coding. 8 gain and offset adjustments gain and offset adjustments are performed with external look ohm, 20 turn potentiometers connected across the :!:15v power supply. the slider of the gain adjustment potentiometer is con- nected to pin 70, and the slider of the offset potentiometer is connected to pin 46. the gain adjustment potentiometer has a range of about :!:20 lsb's, and the offset potentiometer has a range of about :!:10 lsb's. proper gain and offset calibration requires great care, and the use of extremely sensitive and accurate reference instruments. the voltage source used as a signal source must be very stable. it should be capable of being set to within 1/10lsb of the de- sired value at both ends of its range. the gain and offset calibrations will be independent of each other if the offset adjustment (or zero adjustment, if using the 0 to +10v range) is made first. these adjustments are not made with zero and full scale input signals, and it may be help- ful to understand why. an aid converter will produce a given digital word output for a small range of input signals, the average width of the range being one lsb. if the input test signal is set at a point where the converter should be on the verge of switching to the next value, the unit can be calibrated so that it does switch to the next value at just that point. with a high speed convert command rate and a visual display, these adjustments can be performed in a very accurate and sensitive way. analog devices' conversion handbook gives more detailed information on testing and calibrating aid and di a converters. the following table will be useful in calculating the input voltage settings needed during gain and offset calibration. voltage equivalent of ihlsb for converters of various resolutions and input voltage ranges .where range = +f.s. - (-f.s.) offset (or zero) calibration set the input voltage precisely to ~lsb above zero when using the 0 to +10v range, or to ~lsb above nominal minus full scale when using either the :!:5v or :!:10v range. then adjust the offset potentiometer until the converter is just on the verge of switching between all "o's" and having just its lsb on. gain calibration set the input voltage precisely to a value equal to ~lsb less than the point where the converter would have all bits at a logic "i". note that this is i~lsb's less than nominal full scale. for example, full scale of a 0 to +10v 12 bit aid con- verter is actually +9.9976 volts. gain adjustment should be made with an input ~lsb less than that value, or +9.9963 volts. adjust the gain potentiometer to the point where the last bit just comes on. in a 12 bit converter, this would be where the output code just barely changes from 111111111110 to 111111111111. clock inhibit connections clock inhibit (pin 37) normally must be externally jumpered to status (pin 38). the only exception to this would occur when it is desired to short cycle the converter (i.e., have it perform a conversion of less than the maximum number of bits). in such an instance, pin 37 would instead be jumpered to the n + 1 bit output, where n is the number of bits in the conversion. for example, the 12 bit adc1103-o03 would perform 7 bit conversions if pin 37 were jumpered to the bit 8 output (pin 25). the conversion time would be 7/12 x 3.5j.ls max = 2.041ls max. when operating the converter in the short cycle mode, the status (pin 39) and status (pin 38) outputs are no longer valid. instead, the n + 1 bit output becomes a status output (i.e., "0" during a conversion). wiring considerations because of the adc1103's very high speed and its 12 bit capability, good wiling practices are essential for best per- formance. care should be taken to ensure that the analog ground connection is a good, solid connection. the digital inputs and outputs should be kept away from the analog sig- nals. analog ground and digital ground are tied together in- ternally, but it is important that no digital ground signals be present in a path serving as an analog ground return. when de- -3- input range connect input connect in volts signal to pin 49 to 0 to +10v pin 47 pins 54 and 55* -5v to +5v pin 47 pin 72 -10v to +10v pin 48 pin 72 converter input voltage range. resolution 5 volts 10 volts 20 volts 8 bits 9.77mv 19.53mv 39.06mv 10 bits 2.44mv 4.88mv 9.77mv 12 bits 0.61mv 1.22m v 2.44mv obsolete
signing a pc board to accept the adc 11 0 3, it is suggested that as much ground plane area as possible be left underneath the adcl1o3. the +5v and :t15v power inputs are internally bypassed, but it is recommended that additional bypass capacitors be added externally. the capacitors should be located as near the module pins as possible. the +5v bypass capacitor should be connected between the +5v input (pin 1) and digital ground (pin 2). the :t15v bypass capacitors should be connected between pin 4 and analog ground, and pin 6 and analog ground. the capaci- tors would typically be 10j.lf (or greater) tantalum types. recommended power supplies the adcll03 requires +15 volts at 85ma max, -15v at 80ma max, and +5v at 525ma max. analog devices'model902 :t15v modular power supply is rated at 100ma, making it an ideal choice for the adcl1o3's :t15 volt power requirements. analog devices' model 905 modular power supply puts out +5v at up to 1.0 amperes, which makes it well suited to sup- plying the adcll03's +5v needs. the model 902 is priced at $49 (1-9) and the model 905 is priced at $69 (1-9). improving power supply rejection most of the power supply sensitivity called out in the specifica- tions is due to variations in the voltage applied to the gain and offset adjustment potentiometers. this specification can there- fore be improved by at least an order of magnitude by using the circuit shown below in figure 2. 3300. :': 5% +15v to pin 46 to pin 70 in825's 1o0k0. 20 turn offset adj -15v 330r2:':5% figure 2. zener diode isolated adjustment pots serial output the standard adcll03 does not include a serial output. for this reason, serial output (pin 58) and data strobe (pin 61) do not appear on the standard unit. the conversion time on any units containing a serial output is increased by about 20nslbit. the data is transmitted msb first, and the coding is natural binary for a unipolar input, or offset binary for a bipolar input. each serial data bit is valid begin- ning 16ns prior to the rising edge ("0" to "1" transition) of its strobe pulse. this permits the serial data to be clocked into a receiving shift register on successive strobe pulse rising edges. each of the strobe pulses is between 16ns and 22ns wide, and in a complete conversion there are exactly as many strobe pulses as there are bits. the ac1549 mounting card the adcii03's very high speed demands that considerable thought be given to the wiring connected to the module, even when simply evaluating the unit in a temporary laboratory bench set-up. to assist with such evaluations, an ac1549 mounting card is available. this 4v2" x 6" printed circuit card has sockets that allow an adcllo3 to be plugged directly onto it. it also has provisions for an analog devices' model 48 fast settling op amp which, if used, serves as an input buffer. the card includes gain and offset adjustment potentiometers, and power supply bypass capacitors, it mates with a cinch 251-22-30-160 (or equivalent) edge connector, which is supplied with the card. repetitive conversions when making repetitive conversions, a small time interval must be allowed between the completion of one conversion and the beginning of the next. this results in a maximum throughput rate of 769khz for the adcll03-o01, 526khz for the adcll03-o02 and 250khz for the adcll03-o03. the adcll03 can be interrupted during a conversion with a new convert command. the unit will reset and begin a new conversion. however, if it is so interrupted, the convert command pulse should be at least 300ns wide for the adcll03-o01, at least 400ns for the adcll03-o02, and at least 5"ons wide for the adcll03-o03. this will give the adcll03's clock sufficient time to reset before beginning the new conversion. high throughput rate data acquisition the adcll03's high speed allows it to be used in data acquisition applications where a high throughput rate is re- quired. for example, figure 3 shows a sequentially addressed, eight channel data acquisition subsystem capable of acquiring data to 12 bit accuracy at a 220khz throughput rate. the system uses an analog devices' mpx-8a multiplexer, sha-2a sample-and-hold amplifier, and an adcll03-o03. its sampling rate/channel is a very respectable 27.5khz. when using this system, the convert command should be at least 500ns wide. this allows the sha-2a to settle to 12 bit accuracy before the adci103 commences its conversion. the sha-2a is switched into the hold mode on the rising edge of the convert command pulse, but the conversion does not actually begin until the falling edge of the convert command pulse occurs. the mpx-8a is advanced to the next channel at the same time the sha-2a is switched into the hold mode. this allows the multiplexer to settle to a new analog input while the conver- sion of the previous channel's input is in progress. in this way, the mpx-8a's settling time does not affect the maximum throughput rate. convert commano aoo1103 [ 0 1 analog ~ input channels ~ busy signal to computer 10 12 is ,., ,. .2 21 input!.,.,." ~~ 27 30 32 3. oigital output s~~3:~::'l ""- channel.aooress counter figure 3. high speed data acquisition subsystem -4- . v f'o ~ i 0 - i cq ;;; - u 8 ~ !j1 ::> z ci w ~ z a: a. . obsolete
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